1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a voltage generator circuit for use in semiconductor memory devices having circuits which use higher DC voltages than the external power source.
2. Description of the Prior Art
Recently, there are significant trends toward higher-integration, larger-capacity semiconductor memory devices as the development of microprocessing techniques for semiconductors has surged forward. Particularly, in the field of dynamic memories (DRAMs) of semiconductor memory devices which allow random access, samples of 256-mbit DRAMs are being shipped, and gigabit-level DRAMs are being presented at academic meetings. Keeping pace with the progress of such semiconductor memory devices, the voltage supplied to memory devices from external power sources is becoming lower. For example, a source voltage of 5.0 V is used for 16-mbit DRAMs, and a source voltage of 3.3 V for 64 mbit DRAMs. Such reduction in source voltage must also be achieved to ensure the reliability of minute, larger-capacity semiconductor memory devices, by way of prevention of breakdown of gate oxide thin films, time-varying transistor characteristics, etc.
In particular, the technique for lowering external power sources (external line voltages) in the chips to produce the inner source voltages may be applied to DRAMs. The use of lower and more stable inner line voltages than the external source voltages ensures adequate reliability of the devices. In the case of DRAMs, however, in order to write high-level (hereunder abbreviated to "H-level") voltages (equal to the inner source voltages) to the capacitors of the memory cells, higher voltages than the H-level write voltages, that is, the total of the H-level write voltages and the threshold voltages of the transistors, must be applied to the word lines of the memory cells. Therefore, higher and more stable voltages than the external source voltages must be generated even with the ever-lowering level of the source voltages for memory devices. The circuits for generating voltages to be applied to the word lines, etc. by increasing the source voltages are called voltage generator circuits.
An example of prior art boosted-voltage generator circuits is the boosted-voltage generator circuit disclosed in Japanese Unexamined Patent Application Disclosure HEI 5-217372, which is shown in the block diagram of FIG. 1. Referring to FIG. 1, in the circuit shown in the drawing, a booster circuit section 302 performs a pumping operation in response to an oscillation output .phi.OSC from an oscillator 200. The oscillator 200 is normally under control of a V.sub.pp sensor circuit 100 which senses that the output voltage V.sub.OUT is lower than a predetermined boosted-voltage V.sub.pp. When the output voltage V.sub.OUT becomes lower than the predetermined V.sub.PP, the V.sub.PP sensor signal .phi..sub.PP is activated to actuate the oscillator 200. When the output voltage V.sub.OUT has reached the predetermined V.sub.PP, the signal .phi..sub.PP is deactivated through the V.sub.PP sensor circuit 100 to suspend the oscillator 200.
The operation of the boosted-voltage generator circuit shown in FIG. 1 will now be described in detail. FIG. 2 is a circuit diagram of the booster circuit section 302 in the block diagram of FIG. 1. FIG. 3 is a timing chart illustrative of the waveforms during a voltage-boosting operation. Referring to FIG. 1 through FIG. 3, when an H-level signal .phi..sub.OSC is input from the oscillator 200, an H-level signal is output from an inverter 124 via a NAND gate 114. Here, a voltage precharged to the vicinity of the source voltage V.sub.CC of a node N.sub.12 is boosted to the vicinity of 2V.sub.CC by a coupling capacitor C.sub.13. Likewise, an H-level signal is output from an inverter 128, and a voltage precharged to the vicinity of the line voltage V.sub.CC of a node N.sub.14 is boosted to the vicinity of 2V.sub.CC by a coupling capacitor C.sub.14. An output transistor M.sub.12 is then brought into conduction with an output terminal 7 thereby to boost the output voltage V.sub.OUT. Here, a transistor M.sub.32, inputting the voltage across the node N.sub.12 to the gate is brought into conduction with a power supply terminal 8 thereby to precharge the voltage across a node N.sub.11 to the vicinity of the line voltage V.sub.CC. In addition, a transistor M.sub.36 inputting the voltage of the node N.sub.14 to the gate is brought into conduction with the power supply terminal 8 thereby to precharge the voltage across a node N.sub.13 to the vicinity of the line voltage V.sub.CC.
Then, when a low-level (hereunder abbreviated to "L-level") signal .phi..sub.OSC is input from the oscillator 200, L-level signals are output from the inverters 124 and 128 via the NAND gate 114. Subsequently, the voltage across the node N.sub.12 drops to lower than V.sub.CC by a coupling capacitor C.sub.13 and the voltage across the node N.sub.14 drops to V.sub.CC by a coupling capacitor C.sub.14, thereby bringing the transistor M.sub.12 out of conduction with the output terminal 7. An H-level signal is output from an inverter 122 via a NOR gate 113. Here, the voltage across the node N.sub.11 which has been precharged to the source voltage V.sub.CC, is boosted to the vicinity of 2V.sub.CC by a coupling capacitor C.sub.12. Likewise, an H-level signal is output from an inverter 126, and the voltage across a node N.sub.13 which has been precharged to the vicinity of the source voltage V.sub.CC has a voltage boosted to the vicinity of 2V.sub.CC by a coupling capacitor C.sub.14. An output transistor M.sub.11 is then brought into conduction with the output terminal 7 thereby to boost the output voltage V.sub.OUT. Here, a transistor M.sub.33 inputting the voltage across the node N.sub.11 to the gate is brought into conduction with the power supply terminal 8 thereby to precharge the node N.sub.12 to the vicinity of the source voltage V.sub.CC. In addition, a transistor M.sub.37 inputting the voltage across the node N.sub.13 to the gate is brought into conduction with the power supply terminal 8 to precharge the node N.sub.14 to the vicinity of V.sub.CC.
In this way, the two output transistors M.sub.11 and M.sub.12 are alternately brought into conduction with the output terminal 7 in response to complementary signals depending on the oscillation outputs from the oscillator 200, to successively perform the voltage-boosting operation.
The prior art boosted-voltage generator circuit illustrated in FIG. 1 and FIG. 2 has the problems of big fluctuations of the output voltage, and much time spent to recover a predetermined value. The problems will now be explained.
First, when an boosting operation is initiated in the prior art circuit, a drop in the output voltage V.sub.OUT is sensed by the sensor circuit 100 which activates a sensor signal .phi..sub.PP and the oscillator 200 is actuate by the sensor signal .phi..sub.PP. An oscillation output .phi..sub.OSC is then input from the oscillator 200 to a booster circuit section 302 to boost the output voltage V.sub.OUT to the predetermined value V.sub.PP. Therefore, there is a time lag due to the time lapsed until the oscillator 200 starts to oscillate, between the time at which a drop in level of the output voltage V.sub.OUT is sensed and the time at which the booster circuit section 302 is actuated to initiate a voltage-boosting operation. As a result, the output voltage V.sub.OUT greatly drops depending on the time lag, and thus much time is required to restore the voltage to the predetermined V.sub.PP. On the other hand, when the voltage-boosting operation is suspended, after the output voltage V.sub.OUT has reached the predetermined value V.sub.PP as a result of the voltage-boosting operation mentioned above, the sensor signal .phi..sub.PP is deactivated through the sensor circuit 100 to suspend the oscillator 200. Therefore, oscillation outputs, which have been output until the oscillator 200 is suspended after the sensor signal .phi..sub.PP has been deactivated, are input to the booster circuit section 302, thereby excessively boosting the voltage. As described above, the delay in response of the operation of the booster circuit section 302 to the fluctuations of the output voltage V.sub.OUT causes the process of return to the predetermined value V.sub.PP to be delayed and the voltage to be excessively boosted, and this results in great fluctuations of the output voltage V.sub.OUT.
In addition, although the booster circuit section 302 illustrated in FIG. 2 has the advantage of being capable of using the voltage across a node which has been boosted by the capacitor on any one side to precharge the respective nodes on the other side, the precharging power is not sufficient. Accordingly, the voltage-boosting power is insufficient, and thus much time is spent to recover the predetermined value. Let us consider the operation of the transistor M.sub.12, for example. The voltage across the node N.sub.12 is boosted to the vicinity of 2V.sub.CC. The voltage across the node N.sub.12 is applied to the gate electrode of the transistor M.sub.32 for precharging the node N.sub.11, to bring the transistor M.sub.32 into conduction. However, when continuity is established between the drain electrode (node N.sub.12) of the transistor M.sub.12 and the output terminal 7 as a result of boosting the node N.sub.14 to 2V.sub.CC, the voltage across the node N.sub.12 which has been boosted to 2V.sub.CC plunges to V.sub.PP. As a result, the capability of the transistor M.sub.32 is degraded, and this causes the voltage across the precharged node N.sub.11 to fall to lower than the line voltage V.sub.CC. The result is lower drain voltage of the output transistor M.sub.11 while a boosting operation is being performed, and the boosting capability of the booster circuit section 302 is insufficient during pumping. The above-described applies to the other output transistor M.sub.12 as well.